Undersökning av energibesparande metoder för multiplikator
ElectronicsMultiplikatorEffektEffektförbrukningPipeliningInterleavingSpänningsskalningVHDLElektronik
In this thesis a number of energy saving methods for a multiplier on algorithmic level are investigated. For the investigation a multiplier is constructed in VHDL, after which the circuit's performance is investigated. A number of techniques for reduced power consumption are introduced in the circuit and are then evaluated. The conclusions are that all investigated methods, pipelining, interleaving and voltage scaling, should be maximally made use of in order to minimize the power consumption.